Overview
A ground-up CPU RTL design in SystemVerilog — from combinational building blocks through a fully pipelined processor, with open-source tooling.
What is Yantra?
Yantra (Sanskrit: यन्त्र, "machine/instrument") is a ground-up CPU design project focused on deep digital design learning. Every module is written from first principles in SystemVerilog (IEEE 1800-2017), verified with directed and randomized testbenches, and synthesizable with open-source tools.
The project builds incrementally — starting from combinational primitives like multiplexers and ALUs, progressing through sequential elements, and ultimately targeting a fully functioning pipelined processor.
Motivation
Working on CPU microcode professionally means operating at a high level of abstraction. Yantra strips away those layers — every signal, every pipeline stage, every control decision is deliberate and traceable. It also serves as a teaching vehicle: each module is documented with the design rationale and trade-offs considered.
Goals
- Master digital design fundamentals through hands-on RTL implementation
- Build a complete, well-documented CPU microarchitecture in SystemVerilog
- Develop a robust verification environment with testbenches and formal checks
Platform
- Language: SystemVerilog (IEEE 1800-2017)
- OS: macOS (Apple Silicon)
- Package Manager: Homebrew
Toolchain
The project uses an entirely open-source toolchain, orchestrated by a comprehensive build script (run.sh):
| Tool | Role |
|---|---|
| Icarus Verilog | SystemVerilog simulation (interpreted) |
| Verilator | Fast linting + simulation (compiled C++) |
| Verible | Style linting, formatting, language server (Google) |
| Yosys | Open-source synthesis, schematic viewer |
| netlistsvg | SVG schematic generation from Yosys JSON |
| Surfer | Rust-based waveform viewer (modern, keyboard-driven) |
| uv | Fast Python package manager (for TerosHDL deps) |
| TerosHDL | VS Code IDE extension (integrates all tools above) |