Chip Verification Framework

Overview

An opinionated verification framework that generates UVM testbench scaffolding from register maps and interface specifications. Reduced testbench bring-up time from weeks to days on multiple chip projects.

Problem

Writing UVM testbenches is tedious and error-prone. For every new chip block, engineers spend weeks writing:

• Register model classes
• Sequence libraries
• Scoreboards and checkers
• Functional coverage groups

Most of this is boilerplate that follows predictable patterns from the register specification and interface protocols.

Solution

A Python-based generator that reads structured input (JSON register maps + YAML interface specs) and produces:

1. Register Model — complete uvm_reg_block with fields, access policies, and reset values.
2. Agent Stack — driver, monitor, sequencer, and coverage collector for each interface.
3. Scoreboard — reference model skeleton with transaction matching.
4. Test Suite — base test, reset test, register access test, and random stimulus test.

The generated code follows a consistent style and integrates with CI via a Makefile-based simulation flow.

Key Learnings

1. Code generation must be idempotent. Regenerating over hand-edited files destroys trust. We used protected regions (like // USER CODE BEGIN) to preserve manual edits.
2. Coverage closure is the real metric. Generating tests is easy; generating tests that close coverage holes requires understanding the design intent.
3. Adoption requires documentation. Engineers won't use a tool they can't understand in 15 minutes. We invested heavily in examples and a quick-start guide.

Tech Stack

• SystemVerilog, UVM 1.2
• Python 3 (Jinja2 templating, JSON/YAML parsing)
• Synopsys VCS, Cadence Xcelium
• GitLab CI for regression automation