Part V·Advanced ILP and Out-of-Order Execution·Chapter 60 of 66

Part VAdvanced ILP and Out-of-Order Execution

Power, Frequency, and Thermal

August 3, 2026·27 min read·advanced

The earlier parts of this book treated performance as the primary objective. Chapter 2 introduced Moore’s law, Dennard scaling, and the processor performance equation. The intervening parts on ISAs (Part II), pipelining (Part III), the memory hierarchy (Part IV), and the out-of-order machinery of the preceding chapters of Part V all sized structures with the goal of raising instructions per cycle and clock frequency. The implicit assumption was that power followed performance, that faster always meant better, and that the architect’s job was to extract more performance from any silicon budget.

That assumption ended in the mid-2000s. Chapter 2 documented the end of Dennard scaling around 2005. The flat-line in single-thread frequency from that point onward is the most visible consequence. The deeper consequence is that every modern processor now spends as much engineering effort on power management as it does on raw performance. The voltage regulator, the on-chip clock controllers, the thermal sensors, the per-domain power gates, the workload classifiers, and the firmware that runs DVFS are not afterthoughts. They are co-equal with the rename stage and the issue queue in the design of a 2026-era out-of-order core.

This chapter revisits the power equation at the scale of a modern OoO core. It walks the voltage-frequency curve, derives why dynamic voltage and frequency scaling pays for itself, examines race-to-idle as the policy that emerges when static power dominates, surveys dark silicon as the unavoidable consequence of the failure of Dennard scaling, and traces thermal throttling and turbo boost as the two faces of the same opportunistic power-budget allocation. The chapter closes with the AVX-512 frequency cliff as a concrete case study of how vector width interacts with the power-management subsystem on Intel server cores.

01.The Power Equation Revisited

The dynamic power dissipated by a CMOS gate that switches its output is

$P_{\mathrm{dyn}} = \alpha \, C \, V_{\mathrm{dd}}^{2} \, f,$

where $\alpha$ is the activity factor (the fraction of cycles in which the gate switches), $C$ is the load capacitance the gate drives, $V_{\mathrm{dd}}$ is the supply voltage, and $f$ is the clock frequency. The total dynamic power of the chip is the sum of this term across every switching gate, plus a contribution from clock-tree distribution.

The static (or leakage) power is

$P_{\mathrm{stat}} = V_{\mathrm{dd}} \, I_{\mathrm{leak}}(T, V_{\mathrm{dd}}, V_{\mathrm{th}}),$

where $I_{\mathrm{leak}}$ depends exponentially on temperature $T$ , on the supply voltage $V_{\mathrm{dd}}$ , and on the threshold voltage $V_{\mathrm{th}}$ of the transistors. Leakage rises rapidly with temperature, which is one reason a hot chip is also a less efficient chip.

Three observations follow directly from the equation above and shape every design choice in this chapter.

First, the dynamic-power term is quadratic in voltage and linear in frequency. Halving voltage reduces dynamic power by a factor of four. Halving frequency reduces dynamic power by only a factor of two. This asymmetry is the foundation of DVFS: dropping voltage is much more valuable than dropping frequency.

Second, the maximum sustainable frequency at a given voltage follows the alpha-power law, roughly $f_{\max} \propto (V_{\mathrm{dd}} - V_{\mathrm{th}})^{\alpha} / V_{\mathrm{dd}}$ , where the exponent $\alpha$ is close to $2$ for long-channel devices and falls to roughly $1.3$ at the velocity-saturated short-channel transistors of modern nodes. Reducing voltage forces a reduction in frequency, and because the exponent sits below two, the frequency bought by each additional increment of voltage shrinks as the supply rises. Read the other way around, the voltage a target frequency demands climbs faster and faster as that target rises, which is the convexity captured in the voltage-frequency curve plotted in Figure 1.

Figure 1. Voltage-frequency curve sketch for a modern out-of-order core. The plotted curve flattens as the supply rises, so each further increment of frequency costs more voltage than the last. Doubling f_{} from 1 GHz to 2 GHz costs a modest voltage increase. Doubling again from 2 GHz to 4 GHz costs a much larger increase, with dynamic power growing roughly as the cube of frequency in this regime. The shaded steep region is where turbo modes operate.

Third, static power does not depend on activity factor. A chip that sits idle at $V_{\mathrm{dd}}$ with $f$ set to zero still leaks. To reduce leakage when a block is idle, the architect must power-gate the block, cutting its $V_{\mathrm{dd}}$ to zero rather than just its clock.

Worked example: superlinear scaling at the high end

A core operates at $(V_1, f_1) = (0.8 \text{ V}, 2.0 \text{ GHz})$ with a measured dynamic power of $20$ W. The architect proposes to raise the operating point to $(V_2, f_2) = (1.0 \text{ V}, 3.0 \text{ GHz})$ . Estimate the new dynamic power, assuming the activity factor and switched capacitance are unchanged.

The ratio is $\frac{P_2}{P_1} = \frac{V_2^{2} \, f_2}{V_1^{2} \, f_1} = \frac{(1.0)^{2} \cdot 3.0}{(0.8)^{2} \cdot 2.0} = \frac{3.0}{1.28} \approx 2.34.$ So the new dynamic power is roughly $46.9$ W. The 50% frequency increase comes at a 134% power increase. Dynamic power grows as the full cube of frequency only when the supply voltage rises in proportion to the frequency. Here the voltage rises by 25% while the frequency rises by 50%, so the effective exponent is about $2.1$ rather than $3$ . Even at that exponent the high end of the voltage-frequency curve is brutal for energy efficiency, and this is the regime where turbo boost operates.

02.Dynamic Voltage and Frequency Scaling

DVFS is the runtime mechanism that exploits the curvature of the voltage-frequency relationship. A processor exposes a discrete set of operating points, each a (voltage, frequency) pair pre-validated by silicon characterization. A controller selects among the points to match instantaneous workload demand to instantaneous power and thermal headroom.

Operating points (P-states)

The Advanced Configuration and Power Interface (ACPI) standard names the operating points P-states. P0 is the highest-performance state (maximum voltage and frequency). P1, P2, $\dots$ , are progressively lower-performance, lower-power states. A modern x86-64 core typically exposes 10 to 20 P-states. ARM cores follow the same pattern through their own operating-point tables.

Table 1. Typical P-state table for a desktop core

P-state	Frequency (GHz)	Voltage (V)	Estimated dynamic power (W)
P0	4.5	1.20	95
P1	4.0	1.10	71
P2	3.5	1.00	51
P4	3.0	0.95	39
P6	2.5	0.90	30
P8	2.0	0.85	22
P10	1.5	0.80	14
P12	1.0	0.75	9

Illustrative table only. Actual P-state ranges are microarchitecture-specific. Source: representative values from the Intel SDM [1] and the AMD APM [2].

Who decides the P-state

The controller that decides which P-state is active varies by generation. On older platforms, the operating system’s CPU frequency governor selected the P-state through MSR writes. On modern Intel platforms since Skylake, the hardware power-management unit (HWP) inside the package controls the P-state autonomously, with the OS supplying only a high-level performance hint (EPP, the energy-performance preference). On AMD platforms, P-state Tables are exposed and the OS-side governor still plays a role, with hardware over-ride paths through the System Management Unit (SMU). ARM platforms use the OS’s CPUFreq subsystem with platform-specific drivers.

The HWP / SMU paths are faster than OS-driven DVFS because the hardware reacts on a microsecond time scale rather than a millisecond one. A short burst of work that finishes in a millisecond can be served at P0 and then dropped back to a deep idle state before the OS-driven path would have noticed.

Switching cost

A P-state transition is not free. It takes 10 to 100 microseconds to ramp the voltage regulator’s output and to re-lock the phase-locked loop (PLL) at the new frequency. During the transition, the core typically continues to execute at the old, lower frequency or pauses briefly. The controller has to amortize the transition cost across the workload phase that warranted the change. A controller that switches P-states every microsecond would spend most of its time in transitions and would degrade performance.

The cost has two practical implications. First, P-state transitions have to be infrequent relative to workload phases. A typical production system holds a P-state for milliseconds. Second, fine voltage stepping (separate voltage rails per core) lets one core change voltage without disturbing the others. Modern parts use per-core voltage domains for exactly this reason. Apple’s M-series cores, Intel’s Sapphire Rapids, and AMD’s Zen 4 all expose per-core voltage and frequency control.

03.Race-to-Idle

A counterintuitive result of the equation above is that running faster can save energy. The principle is called race-to-idle: finish the task at the highest available frequency, then drop into the deepest idle state available.

The argument

Energy consumed for a fixed task is

$E_{\text{task}} = P_{\text{active}} \cdot t_{\text{active}} + P_{\text{idle}} \cdot t_{\text{idle}}.$

If $P_{\text{idle}}$ is small (deep sleep state, leakage minimized through power gating), then completing the task quickly so that $t_{\text{idle}}$ stretches over the remaining wall-clock period can produce lower $E_{\text{task}}$ than running slower at a lower $P_{\text{active}}$ for longer. The crossover depends on the ratio between active and idle power.

Example: Race-to-idle versus crawl

A task requires $10^{9}$ cycles of work. Two policies are considered. Policy A (race-to-idle) runs at $4$ GHz drawing $50$ W, finishes in $0.25$ s, then idles at $1$ W for $0.75$ s, for a total energy of $50 \cdot 0.25 + 1 \cdot 0.75 = 13.25$ J over a one-second window. Policy B (crawl) runs at $1$ GHz drawing $10$ W for the full $1$ s, for a total energy of $10$ J. Policy B wins by 25%.

If the idle-state power were $0.1$ W instead of $1$ W, Policy A’s energy would be $50 \cdot 0.25 + 0.1 \cdot 0.75 = 12.575$ J, and Policy B would still win at $10$ J. No reduction in idle power can flip this outcome, because Policy A’s active energy alone is $12.5$ J and that already exceeds Policy B’s total. The fast operating point costs $50~\mathrm{W} / 4~\mathrm{GHz} = 12.5$ nJ per cycle against $10~\mathrm{W} / 1~\mathrm{GHz} = 10$ nJ per cycle for the slow one, and race-to-idle pays only when that per-cycle penalty is small enough for the saved idle energy to cover it, or when the work is bursty enough that the idle interval dominates the window.

When race-to-idle wins and when it loses

Race-to-idle wins when the active workload has a low average utilization. A core that is busy for 10% of the time and idle for 90% benefits from completing each burst quickly and idling deeply. The deeper the idle state, the larger the savings.

Race-to-idle loses when the workload is sustained or near-saturated. A core that is busy 90% of the time and idle 10% sees almost all its energy spent in the active state, where the cubic frequency scaling on the voltage-frequency curve dominates. Running at a lower frequency saves more than racing-to-idle does.

A second consideration is the cost of entering and exiting deep idle states. A C-state transition can take tens to hundreds of microseconds, and during the transition the core is neither doing useful work nor saving the full idle-state power. If the average idle interval is shorter than this transition latency, the controller does not enter the deep state, and race-to-idle loses its argument.

Modern firmware blends the two strategies. The HWP / SMU controller estimates workload utilization on a microsecond time scale and biases toward race-to-idle for short bursty workloads, toward sustained mid-frequency operation for steady workloads, and toward deep low-frequency operation for background and unimportant work. The energy-performance preference hint (EPP) lets software bias the controller’s decisions for the active process class.

04.Dark Silicon

The end of Dennard scaling is the deepest reason power-management became a first-class concern. Dennard’s 1974 paper showed that as transistor dimensions shrink by a factor $k$ , the supply voltage also shrinks by $k$ , so per-transistor power drops as $1/k^{2}$ . Doubling the transistor count per unit area at the next node therefore leaves total power per unit area roughly unchanged. From the 1970s through the early 2000s this held to good approximation. Each new node delivered more transistors at the same power.

Why Dennard scaling ended

Two physical phenomena ended Dennard scaling around the 65 nm node. First, subthreshold leakage grew exponentially as $V_{\mathrm{th}}$ had to be lowered to keep up with $V_{\mathrm{dd}}$ . By the 90 nm node, leakage was a substantial fraction of total chip power. Second, gate-oxide tunneling currents added a second leakage mechanism. The transistors could no longer be turned fully off without sacrificing speed.

The combined result is that the supply voltage cannot continue to scale down with transistor dimensions. $V_{\mathrm{dd}}$ has been roughly flat between 1.0 V and 1.2 V for the past fifteen years. Each new node doubles transistor density, but per-transistor power no longer falls by the full $1/k^{2}$ factor. Total chip power budget grows with each generation if every transistor is to be active.

The dark silicon argument

Power is bounded by package thermal design power (TDP), which is roughly fixed by the cooling solution and the form factor. If per-transistor power does not fall fast enough, then each new generation produces a chip with more transistors than can be active simultaneously within the TDP. The fraction that must be unpowered at any one time is the dark silicon fraction.

The architectural responses to dark silicon are several. First, heterogeneous integration: include large blocks of fixed-function accelerators that are turned off most of the time. Each accelerator sits dark when it is not needed and consumes near-zero power. Second, aggressive power gating: every core, every cache slice, and every accelerator block has dedicated power gates that fully shut off its supply when idle. Third, dynamic voltage and frequency scaling on the active blocks to keep the active fraction within the TDP envelope. Fourth, turbo boost, which redirects the TDP budget from idle blocks to active blocks for short windows.

The shift to many smaller specialized blocks rather than a few large general-purpose cores is a direct consequence. The big.LITTLE architectures from ARM (see Chapter 16), the P-core / E-core split on Intel client parts since Alder Lake, and the GPU-plus-NPU-plus-CPU heterogeneity on Apple’s M-series chips are all responses to the dark-silicon constraint.

05.Thermal Throttling

The thermal subsystem is the safety net that prevents the chip from destroying itself. Every modern processor carries on-die temperature sensors that report die temperature to the power-management unit on a microsecond time scale. When the temperature exceeds a threshold (Tjmax, the maximum junction temperature, typically $100\degree{}\mathrm{C}$ on x86-64 parts and $105$ - $115\degree{}\mathrm{C}$ on ARM parts), the hardware automatically reduces frequency, voltage, or both, until the temperature falls back into the safe range.

Sensor placement and accuracy

The on-die temperature sensors are placed near the hottest expected hotspots. On a multi-core chip there is typically one sensor per core, plus several sensors near the L3 cache, the memory controller, and the I/O blocks. The PMU polls all sensors at a high rate (kHz range) and uses the highest reading to drive the throttle decision. The cores are not independent: one core hitting Tjmax forces package-wide throttling, since the heat from that core spreads to its neighbors.

The accuracy of the sensors is finite. The reported temperature can lag the actual transient temperature by a few microseconds, which is short compared to thermal time constants of milliseconds but long enough that the PMU must include margin in its throttle threshold. Setting the throttle threshold too high risks transient overshoot. Setting it too low gives up performance.

Throttle response

The two levers the PMU has are voltage and frequency. The standard response is to step down the active P-state to a less aggressive operating point. If the temperature continues to climb, the PMU steps further down. In emergency conditions (sensor failure, runaway thermal event), the PMU asserts a hardware signal called PROCHOT (Intel terminology) or its equivalent on other vendors, which forces the core to clock-gate large fractions of the pipeline and idle aggressively. PROCHOT is a defensive measure, not a performance feature.

Skin temperature and laptops

Laptops and mobile devices add a second thermal constraint: the surface temperature where the user touches the device must stay below a comfort threshold (typically $45\degree{}\mathrm{C}$ for skin contact). The chip can be well within Tjmax and still be forced to throttle because the laptop chassis is too hot.

Apple’s M-series cores, which run in fanless or low-fan-power configurations in the MacBook Air, are particularly sensitive to the skin-temperature constraint. The cores often throttle before they reach Tjmax. Pro variants with active cooling can sustain higher sustained performance at the same Tjmax simply because the fan keeps the surface within comfort range.

06.Turbo Boost

Turbo boost is the mirror image of thermal throttling. When the chip has thermal and power headroom, the PMU opportunistically raises the frequency of active cores above the nominal base frequency. The headroom typically appears when some cores are idle or when a sustained workload has not yet heated the package.

Turbo bins

Turbo states are organized as turbo bins, each one a small frequency step (100 MHz to 200 MHz on modern parts) above the base frequency. The PMU selects the highest bin that satisfies all of (a) the temperature is below Tjmax minus a margin, (b) the package power is below the package thermal design power minus a margin, (c) the current is below the maximum sustainable current the voltage regulator can deliver, and (d) the number of active cores is at or below the per-bin active-core count limit.

The active-core count limit is the source of the per-bin specification on most Intel parts. A part rated "5.5 GHz boost on 1 core, 5.2 GHz on 2 cores, 4.9 GHz on 4 cores, 4.6 GHz on all cores" exposes the constraint plainly. Boosting more cores requires more total power, which forces a lower per-core frequency to stay within the TDP budget.

Table 2. Representative turbo bins on a desktop CPU

Active cores	Max frequency (GHz)	Estimated package power (W)
1	5.5	60
2	5.2	90
4	4.9	130
8	4.6	170
16	4.3	200

Illustrative table. Actual turbo bins are documented per SKU in vendor spec sheets [1][2].

Time-windowed power budgets

Intel’s PL1, PL2, PL3, PL4 power-limit hierarchy exposes the time-windowed budget mechanism. PL1 is the sustained power limit, typically equal to TDP, applied over a long time window (28 seconds is a common default). PL2 is the short-term burst limit, higher than PL1, applied over a shorter window (10 to 100 milliseconds). PL3 and PL4 cover instantaneous current limits.

The mechanism lets the part exceed its nominal TDP for short bursts. A user clicking a button that triggers a one-second compute burst can see the chip boost to PL2 power for that burst, exceeding the sustained PL1 limit. The chip averages PL1 over the long window, so sustained workloads see only the nominal power. The PMU integrates the energy delivered, and when the long-window integral catches up to the average TDP budget, it forces the chip back to the lower power level.

AMD exposes the equivalent through Package Power Tracking (PPT), Thermal Design Current (TDC), and Electrical Design Current (EDC) limits.

Predicting turbo behavior

Turbo behavior on real workloads is not deterministic. The starting temperature of the chip, the surrounding ambient temperature, the fan curve, the workload’s instantaneous current draw, and the distribution of activity across cores all affect which bin the PMU selects. Benchmark numbers reported as "boost frequency" reflect the maximum the part can hit under ideal conditions. Sustained turbo behavior on a saturated chip rarely exceeds the all-cores boost bin.

07.AVX-512 Frequency Cliffs

A widely-documented case where vector width interacts directly with the power-management subsystem is Intel’s AVX-512 implementation on Skylake-SP and successor server cores. The 512-bit vector data paths draw substantially more current per cycle than scalar code, because they switch eight times as many lanes per instruction. The voltage regulator and the maximum sustained current limit cannot support full base frequency when AVX-512 is in use.

The cliff

When the core detects AVX-512 issue activity, the PMU drops the operating point to a lower P-state called AVX-512 license level 2 (in contrast to license level 0 for scalar code and license level 1 for AVX2). The frequency drop is microarchitecture- and SKU-specific, ranging from 200 MHz to 600 MHz below the nominal turbo, with a corresponding voltage reduction.

The cliff is automatic. The PMU monitors the AVX-512 active state through a hardware counter that increments when a 512-bit vector operation issues. After a threshold of consecutive issues, the PMU steps down. After a hysteresis period of scalar-only activity, it steps back up.

Why the cliff exists

The cliff exists because the chip’s voltage regulator cannot deliver the current required by AVX-512 at the nominal high-frequency operating point without exceeding the safe transient current limit (EDC on AMD, ICCMAX on Intel). The PMU has two choices when a wide-vector instruction issues: reduce frequency, or risk exceeding the current limit and triggering an emergency throttle (PROCHOT). The pre-validated lower P-state is the controlled response.

Mitigations and workarounds

Several mitigations exist. The compiler can be told to avoid AVX-512 entirely in code paths that mix with non-AVX-512 work. Intel’s later parts (Ice Lake server, Sapphire Rapids) have narrowed the cliff substantially by improving the voltage regulator and reducing the steady-state penalty. The penalty is no longer the 600 MHz that Skylake-SP imposed. Ice Lake server reports a penalty of around 100-200 MHz.

The Arm Scalable Vector Extension (SVE) and SVE2 take a different approach: the vector length is implementation-defined and can be narrower on cores that cannot sustain the full vector width without throttling. The chip never advertises a vector width it cannot sustain. This avoids the cliff at the cost of variable performance across implementations of the same ISA.

08.Power-Aware Microarchitectural Choices

The power equation interacts with most architectural choices made in Part V. Several patterns recur.

Clock gating

The cheapest power optimization is to stop the clock to any pipeline stage that is not doing useful work in a given cycle. A bubble cycle in the execute stage does not need the ALU clock to toggle. The result is a dynamic power saving proportional to the bubble fraction. Every modern OoO design clock-gates at the granularity of individual issue ports, register-file banks, and ROB entries. The infrastructure is invisible to software but contributes substantially to the active power.

Power gating

The cousin to clock gating is power gating: cutting $V_{\mathrm{dd}}$ to a block that is not in use. Power gating eliminates both dynamic and static power for that block, at the cost of taking the block offline. The entry and exit latency is typically a few microseconds, so power gating is reserved for blocks expected to be idle for at least that long. Idle cores, idle accelerator blocks, and idle cache slices on the last-level cache are common power-gating candidates.

Width and depth tradeoffs

Wider pipelines (more issue ports, more rename slots, more execute units) extract more ILP but also draw more current per cycle. Deeper pipelines reach higher frequencies but pay a quadratic penalty in dynamic power because the per-stage capacitance is amortized over more cycles per instruction. The optimal point is workload-dependent and is one reason heterogeneous cores (P-cores and E-cores on Intel client parts, big.LITTLE on ARM) have displaced uniform-core designs in client SoCs.

Specialization

The fastest growing power-saving technique is to add a fixed-function accelerator for a common operation. A dedicated video codec engine, a dedicated AES instruction unit, or a dedicated neural-network engine performs the operation at one tenth to one hundredth of the energy per operation of the general-purpose core. The accelerator sits dark when not in use and consumes negligible power. Apple’s Secure Enclave, Apple’s NPU, and the cryptographic acceleration instructions in AArch64 are examples. Part VIII covers domain-specific accelerators at length.

09.Worked Examples

Example: P-state energy comparison

A workload requires $4 \times 10^{9}$ cycles. The CPU has three P-states: $(V_0, f_0) = (1.2 \text{ V}, 4 \text{ GHz})$ drawing $80$ W active, $(V_1, f_1) = (1.0 \text{ V}, 3 \text{ GHz})$ drawing $40$ W active, and $(V_2, f_2) = (0.8 \text{ V}, 2 \text{ GHz})$ drawing $20$ W active. Idle power is $2$ W in all cases. The workload must finish within $2$ s. Which P-state minimizes total energy?

Solution. At $f_0 = 4$ GHz, the active time is $4 \times 10^{9} / 4 \times 10^{9} = 1$ s. Idle time is $1$ s. Energy is $80 \cdot 1 + 2 \cdot 1 = 82$ J.

At $f_1 = 3$ GHz, the active time is $4/3 \approx 1.33$ s. Idle time is $0.67$ s. Energy is $40 \cdot 1.33 + 2 \cdot 0.67 \approx 54.7$ J.

At $f_2 = 2$ GHz, the active time is $2$ s. Idle time is $0$ s. Energy is $20 \cdot 2 = 40$ J.

The lowest P-state wins on energy here because it is also the cheapest per unit of work. P0 buys $4$ GHz for $80$ W, which is $20$ nJ per cycle, while P2 buys $2$ GHz for $20$ W, which is $10$ nJ per cycle. Race-to-idle cannot close that gap at any idle power. Even if the idle state drew nothing at all, P0 would still spend $80$ J against P2’s $40$ J.

Example: Thermal time constant

A core in a fanless laptop has a thermal capacitance of $5$ J/K and dissipates heat to ambient through a thermal resistance of $2$ K/W. The chip starts at ambient ( $25\degree{}\mathrm{C}$ ) and begins drawing $20$ W of power. Compute the steady-state temperature, and estimate how long it takes to reach $60\degree{}\mathrm{C}$ .

Solution. The steady-state temperature rise is $\Delta T = P R = 20 \cdot 2 = 40$ K, so the steady-state junction temperature is $25 + 40 = 65\degree{}\mathrm{C}$ . The thermal time constant is $\tau = R C = 2 \cdot 5 = 10$ s.

The temperature follows $T(t) = 25 + 40 (1 - e^{-t/10})$ . Setting $T = 60$ gives $35 = 40(1 - e^{-t/10})$ , $e^{-t/10} = 0.125$ , $t = 10 \ln 8 \approx 20.8$ s.

The core can sustain $20$ W draw for about 20 seconds before the PMU is likely to begin throttling at $60\degree{}\mathrm{C}$ . This is why short bursts of work hit turbo frequencies easily while sustained workloads settle at lower frequencies.

10.Exercises

Exercises

Power scaling. A core dissipates $30$ W at $(1.0 \text{ V}, 3 \text{ GHz})$ . Compute its dynamic power at $(1.1 \text{ V}, 3.5 \text{ GHz})$ . Compute at $(0.9 \text{ V}, 2 \text{ GHz})$ . Comment on the asymmetry.
P-state selection. Given the table of the table below, compute the energy required to complete a $3 \times 10^{9}$ cycle workload at each P-state, assuming idle power of $1.5$ W. Which P-state minimizes energy if the deadline is $1.5$ s? If the deadline is $0.8$ s?
Race-to-idle threshold. Derive an algebraic condition on the ratio $P_{\text{active}} / P_{\text{idle}}$ above which race-to-idle saves energy versus running at half the frequency for double the active time. Assume dynamic power scales as $V^{2} f$ and the supply voltage scales linearly with $f$ .
Dark silicon estimate. A chip has $10^{10}$ transistors. Each transistor draws $40$ nW of average power at full activity in the active state. The package TDP is $200$ W. What fraction of transistors can be active at any one time? What fraction must be dark?
Thermal response. A core’s PMU polls the temperature sensor at $10$ kHz. The thermal time constant of the die is $1$ ms. Discuss whether the sampling rate is adequate to track temperature accurately. What would happen if the sensor were polled at $100$ Hz?
Turbo bin tradeoff. A four-core CPU has turbo bins of $5.0$ GHz on one core, $4.5$ GHz on two cores, $4.0$ GHz on three cores, and $3.5$ GHz on all four cores. A workload has four embarrassingly parallel threads. Each thread requires $X$ cycles to complete. Is running on one core at $5.0$ GHz faster or slower than running on four cores at $3.5$ GHz? Compute the breakeven point.
AVX-512 cliff. A vectorizable inner loop runs at $4.5$ GHz in AVX2 mode at $8$ elements per cycle. In AVX-512 mode the frequency drops to $4.0$ GHz but processes $16$ elements per cycle. The loop body has overhead that runs at the same frequency in both modes. Above what fraction of total time spent in the vector portion does AVX-512 pay off?
Skin temperature. A laptop’s chassis has a thermal resistance of $3$ K/W from the chassis surface to ambient. The maximum acceptable skin temperature is $45\degree{}\mathrm{C}$ and the ambient temperature is $25\degree{}\mathrm{C}$ . What is the maximum sustained power dissipation the laptop can support while keeping the skin within comfort range?
Clock gating coverage. A six-wide rename unit fills three slots on average. Estimate the dynamic-power saving relative to a design without clock gating, assuming the unrenamed slots’ clock paths consume $1.5$ W when ungated and zero when gated.
DVFS transition overhead. A workload phase lasts $100~\mu$ s and is followed by a $1$ ms idle period. A P-state transition takes $50~\mu$ s. Compute the energy saved by transitioning to a lower P-state during the idle period, assuming idle power at the high P-state is $5$ W and at the low P-state is $0.5$ W. Is the transition worth it?

References

[1](2024). “Intel.”
[2](2024). “AMD64.”
[3]Esmaeilzadeh, Hadi and Blem, Emily and St. Amant, Renee and Sankaralingam, Karthikeyan and Burger, Doug (2011). “Dark Silicon and the End of Multicore Scaling.” In Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA), pp. 365--376. doi:10.1145/2000064.2000108

Book mode