SRAM Arrays, Register Files, and Error Correction

01.Part 1, why an RTL engineer has to know the circuit

1.1 The array is the one thing you cannot re-synthesize

Everything else in your block is soft. A path is too slow, so synthesis upsizes a cell, restructures a tree, or place and route shortens a wire. A block is too big, so the tool remaps to smaller cells. That elasticity is the whole reason RTL is a productive way to design.

The array has none of it. An SRAM macro arrives as a hard block with a fixed pin list, a fixed physical outline, fixed timing arcs, a fixed set of legal configurations, and a fixed minimum cycle time. Synthesis will not touch it. Place and route drops it as a rectangle and routes around it. If the macro needs 420 ps to produce data, your block runs no faster than 420 ps no matter how good the rest of your RTL is.

So the array is a fixed point, and the rest of the design bends around it. That inverts the usual mental model. You do not write RTL and then see what timing says. You read the macro datasheet first, decide what fits in a cycle before and after it, and then write RTL that lives inside that budget.

1.2 The datasheet, and the decisions it makes for you

A memory compiler is a program from the foundry or an IP vendor that takes a few parameters and emits a characterized macro plus its models. Here is what it hands back, with a plausible set of numbers for a small array in a modern process, and what each line dictates.

Read the last row again. If you need a byte-granular write and the compiler only offers word writes, that is not a request you can make. You have to build a read-modify-write around the macro in your own RTL, which costs a cycle and creates a hazard you now have to handle. That single missing feature reshapes your store pipeline.

1.3 Six microarchitecture decisions that are really array decisions

The reason this material shows up in a cache or CPU interview is that array physics silently decides things people think of as microarchitecture.

Pipeline depth. An L1 that takes three cycles instead of two changes your load-use penalty, which changes your scheduler's speculative wakeup, which changes your replay machinery. Those three cycles come from Part 3 of this note, not from a design meeting.

Issue width. How many loads per cycle you can support is a question about array ports, and Part 5 shows that ports are the most expensive thing you can ask an array for.

Bank conflict rules. Your arbiter, your stall logic, and your scheduler's assumptions all depend on which simultaneous accesses the array can actually serve, which is a banking question.

Store granularity. Whether a single-byte store costs one array access or a read-modify-write is set by the ECC word size, which is set by the code, which is Part 7.

The DVFS floor. How low the voltage of a whole domain can drop is almost always set by the arrays and not by the logic, which is Part 4 and links straight to DVFS Droop and Thermal.

Whether the machine is allowed to be wrong. How much protection each structure gets, and what happens on an uncorrectable error, is Part 7 and it reaches all the way up into the machine check architecture and the operating system.

You will not draw a bitcell in a CPU design role. You will constantly make decisions whose answer is a bitcell property.

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02.Part 2, the bit cell

2.1 Storing a bit needs a loop

Start with a question so basic it feels silly. How do you make a wire remember?

You cannot. A wire is a capacitor with leakage, and left alone it forgets in microseconds. So a bit needs something actively holding it, and the only mechanism available in CMOS is feedback, meaning an output wired back to an input so the circuit keeps re-asserting what it already believes.

Take the inverter from section 1.1 of Digital Logic and Timing and wire its output to its own input. That fails, because an inverter wants its output to be the opposite of its input, and now they are the same wire. The circuit settles at the one voltage where input equals output, roughly half the supply, and sits there. It has one state and it is a useless one.

Now use two inverters in a loop. Inverter L takes node $Q$ and drives node $QB$. Inverter R takes $QB$ and drives $Q$. Suppose $Q = 0.9$ V. Then L drives $QB$ to 0 V. Then R sees 0 V on its input and drives $Q$ to 0.9 V, which is what we assumed. The assumption reproduces itself, so it is stable. Now suppose $Q = 0$ V. Then $QB = 0.9$ V, and R drives $Q$ to 0 V. Also stable. Two self-consistent states, and the loop holds whichever one it is in as long as the supply is present. That is memory, built from four transistors.

2.2 The 6T cell, drawn

Two more transistors connect the loop to the outside world. They are called access transistors or pass gates, and they are switched by a shared control wire called the wordline. When the wordline is low, they are off and the cell is sealed. When it is high, node $Q$ is connected to a vertical wire called the bitline and node $QB$ is connected to its complement, the bitline bar.

Six transistors. Four for the storage loop, two for access. Nothing else, and that minimalism is the point, because this structure is replicated tens of millions of times on a die and every wasted square nanometre is multiplied by that count.

2.3 Bistability is the same phenomenon as metastability

Plot the two inverter transfer curves on the same axes, one of them with its axes swapped so both live in the $Q$ versus $QB$ plane. The picture that results is called the butterfly curve.

The middle crossing is the same object as the metastable point in Clocking Reset and Domain Crossing. A flip-flop is also built from cross-coupled inverters, and metastability is that flop being pushed onto the middle crossing, where the loop gain is not enough to resolve quickly and the node can linger for an unbounded time. Same structure, same three equilibria, opposite intent. In a flop the middle point is a hazard to be escaped. In an SRAM cell the two outer points are the product and the middle point is what you spend your design margin staying away from.

The static noise margin, written SNM, is how far you can push a stored node before it falls over the middle crossing into the other state. It is measured in millivolts, and every subsequent section of Part 4 is about protecting it.

2.4 SRAM against DRAM, and why the hierarchy has layers

A DRAM cell is one transistor and one capacitor. The capacitor holds charge, the transistor connects it to a bitline. That is it. Two devices instead of six.

The count understates the difference. Area is not proportional to transistor count, it is set by layout, and a DRAM process builds the capacitor vertically, either in a deep trench below the transistor or stacked above it, so the capacitor consumes almost no additional plan-view area. Measured in $F^2$, where $F$ is the process feature size, a DRAM cell is around $6F^2$ and a 6T SRAM cell is around $120$ to $150F^2$. That is a factor of twenty to twenty-five, not a factor of six. Exact comparison is slippery because DRAM and logic are built in different, specialized processes, but the order of magnitude is solid.

Now the consequences, and each one is a reason the memory hierarchy exists.

Put a number on refresh so it stops being an abstraction. A DRAM bank must refresh every row within a retention window of about 64 ms. With 32768 rows in a bank and each refresh taking roughly 45 ns, the bank spends $32768 \times 45\ \text{ns} = 1.47$ ms out of every 64 ms unavailable, which is about 2.3 percent of its time doing nothing but remembering. That fraction grows as capacity grows, and at high temperature the retention window halves roughly every 10 degrees Celsius, so it can reach the high single digits in a hot server part.

The destructive read is worth dwelling on because it has no SRAM analogue. Opening a DRAM row dumps the cell capacitors onto the bitlines, and the sense amplifiers then latch the values and drive them back into the cells. The row of sense amplifiers is therefore acting as a buffer holding the whole row, which is exactly what a DRAM row buffer is and why row hits are cheap and row misses expensive. An SRAM read leaves the cell holding its value because the cross-coupled loop is still powered and still fighting, which is why SRAM has no row buffer concept and no activate-precharge protocol.

So the layering falls out. SRAM is fast, non-destructive, buildable in a logic process, and expensive per bit, so you use a little of it very close to the pipeline. DRAM is slow, destructive, needs refresh, needs its own process, and is cheap per bit, so you use a lot of it far away. There is a middle option, eDRAM, which is DRAM built in a modified logic process and has been shipped as a large last-level cache in some server parts. It buys roughly three times the density of SRAM at the cost of refresh logic on the CPU die and a process adder, and it has largely lost ground to simply building more SRAM on cheaper nodes and to stacked memory.

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03.Part 3, reading, and why sense amplifiers exist

3.1 Count the capacitance before designing anything

The single most important fact about an SRAM read is a ratio, and the ratio is not close.

The bitline is a vertical wire running the full height of the array. Every cell on it contributes the junction capacitance of its access transistor plus its share of the wire. Call that 0.6 fF per cell, an illustrative figure of the right order for a modern process. A subarray with 256 rows therefore presents

$C_{BL} = 256 \times 0.6\ \text{fF} = 154\ \text{fF}$

and once you add the wire itself and the sense amplifier's input, call it 150 fF as a round number.

The cell driving that bitline is two minimum-ish NMOS transistors in series, the access transistor and the pulldown, both deliberately made tiny because they are replicated tens of millions of times. Call the current they can deliver 30 uA.

Now use the delay expression from section 1.2 of Digital Logic and Timing, $t = C \Delta V / I$, and ask how long a full swing takes.

$t_{full} = \frac{150 \times 10^{-15} \times 0.9}{30 \times 10^{-6}} = 4.5 \times 10^{-9}\ \text{s} = 4.5\ \text{ns}$

At 3 GHz that is 13.5 clock cycles, for one read, from a small array. That is catastrophic and it is why the naive picture of reading an SRAM is wrong.

Now ask how long a 100 mV swing takes.

$t_{100mV} = \frac{150 \times 10^{-15} \times 0.1}{30 \times 10^{-6}} = 0.5 \times 10^{-9}\ \text{s} = 0.5\ \text{ns}$

Nine times faster, because $\Delta V$ appears linearly and you asked for one ninth of it. That is the entire trick. Do not wait for the bitline to swing. Wait only until you can tell which way it is going, then have a separate, fast, high-gain circuit finish the job. That circuit is the sense amplifier.

Notice what has just happened conceptually. The array has stopped being purely digital. Somewhere inside it there is a 100 mV analog signal being compared against a reference, and the correctness of your cache depends on that comparison. Everything strange about SRAM follows from this one design decision.

3.2 The four phases, drawn

A read proceeds in four phases. Each one exists for a reason, and skipping any one of them breaks something.

Precharge. Both bitlines are driven to the supply and then released to float. Both, not one, and equalized to each other, because the sense amplifier will compare them and any pre-existing imbalance is indistinguishable from signal. The precharge devices then turn off, leaving both lines floating high on their own capacitance. This is why a cache access has a precharge phase you can see in the timing, and why back-to-back accesses to the same subarray have a minimum spacing that has nothing to do with your pipeline.

Wordline rise. The row decoder drives one wordline high, turning on the access transistors of every cell in that row, all 288 or 512 or 1024 of them. Every one of those cells now begins fighting its own bitline pair. Note that you activated the whole row even though you probably only wanted 64 bits of it, and Part 5 explains why and what it costs in power.

Develop. Inside each cell, one internal node is low. Through its access transistor it drags the corresponding bitline down, slowly, at the rate the arithmetic above gave. The other bitline stays at the precharge level because the cell's other side is high and there is nothing to pull it anywhere. So a differential appears, and its sign encodes the bit. This is the phase whose duration is set by physics rather than by logic design.

Sense. Once the differential is comfortably larger than the sense amplifier's own input offset, the amplifier is enabled. It is itself a cross-coupled pair, the same structure as section 2.3, deliberately started at its unstable middle point and then tipped by the input differential. Positive feedback drives it hard to whichever rail the differential favors, in tens of picoseconds. Out comes a clean digital 0 or 1.

3.3 Why differential and not a threshold

An obvious simplification suggests itself. Precharge one bitline, let the cell pull it down, and compare it against a fixed reference voltage of say 0.85 V. Why keep two bitlines and compare them against each other?

Because almost everything that can go wrong moves both bitlines together and cancels in a difference. Supply noise from a neighboring block couples into both lines. Temperature shifts both precharge levels. Process variation in the precharge devices shifts both. Charge injection when the wordline rises couples into both. A single-ended comparison against a fixed reference sees all of that as signal. A differential comparison rejects all of it, because it is common mode, meaning identical on both inputs.

The remaining error is the sense amplifier's own input offset, meaning the differential voltage at which it is genuinely undecided, caused by mismatch between its own two halves. That offset is a random variable with a standard deviation of perhaps 20 to 30 mV in a modern process, and it is why you wait for 100 mV rather than 30 mV. You are buying sigmas of margin against your own amplifier being crooked, and Part 4's yield arithmetic applies here too.

Single-ended sensing does exist, and it is normal in register files and small arrays where the bitline is short, the read current is large, and the extra bitline track is more expensive than the lost noise immunity. That is a design point, not an error, and Part 5 comes back to it.

3.4 Two consequences that reach all the way up to your RTL

The array is an analog macro, so it is compiled and not synthesized. A sense amplifier's correctness depends on transistor matching, on the exact timing of its enable relative to the wordline, and on the precharge level. None of that is expressible in a standard cell library or checkable by static timing analysis in the ordinary way. If the sense enable fires 30 ps early, the amplifier tips on noise instead of signal and the array returns wrong data on some fraction of accesses at some corner of voltage and temperature. So the array is designed once by circuit designers, characterized exhaustively across corners, and delivered as a hard macro with guaranteed timing. Your synthesis tool is not permitted to have opinions about it. That is the direct answer to why you cannot just write a memory as a SystemVerilog array and let the tool figure it out, and it is a good short answer in an interview.

Develop time does not scale with logic speed, so cache latency in cycles has grown. Logic delay improved with every process node because transistors got faster. Bitline develop time is set by $C_{BL} \Delta V / I_{cell}$, and while $I_{cell}$ improved, $C_{BL}$ per cell fell only slowly and array capacities grew, and $\Delta V$ could not shrink below the sense amplifier's offset, which is set by mismatch and is stubborn. Meanwhile clock periods collapsed. So the same physical access time became more and more cycles.

Those are order-of-magnitude public figures, not any particular part. The trend is the point. Absolute access time barely moved. Cycle count roughly quintupled. Every one of those extra cycles had to be absorbed by microarchitecture, which is where load-use speculation, speculative wakeup, and replay in Out of Order Execution came from, and why Cache Organization and Prefetching spends so much effort hiding latency that used to be free.

3.5 Where an access actually spends its time

Break a single-cycle-equivalent array access into its parts so the budget stops being mysterious. Take a 128-row subarray at 3 GHz, so the cycle is 333 ps.

Read the middle row. Half the access time is one phenomenon, and it is the one you have the least control over. The only levers on it are shortening the bitline, which means more subarrays and more decode and more area, or increasing the cell current, which means bigger cells and less density, or reducing the required differential, which means a better sense amplifier and worse yield. That triangle is the whole of array design and it is why Part 5 looks the way it does.

There is a power consequence too, and it is large. Every access swings the full precharge charge back onto every bitline in the activated columns. Using $E = C V^2$ from section 1.1 of Power Fundamentals and Clock Gating, restoring 150 fF through 100 mV on 288 bitline pairs costs $288 \times 2 \times 150 \times 10^{-15} \times 0.9 \times 0.1 \approx 7.8$ pJ per access, because the precharge devices restore the swung line from the full rail. At one access per cycle at 3 GHz that is 23 mW for one small subarray. Bitline swing is the dominant dynamic power term in an array, which is why arrays are aggressively gated at the subarray level, why only the selected columns are precharged in many designs, and why the clock gating discipline of Power Fundamentals and Clock Gating applies with even more force to arrays than to logic.

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04.Part 4, writing, the margin conflict, and the voltage floor

4.1 Writing means losing a fight on purpose

A read is designed so the cell barely disturbs the bitline. A write is the opposite. The write drivers grab both bitlines and drive them hard, one to ground and one to the supply, in the pattern you want stored. Then the wordline rises and the access transistors connect those driven bitlines to the internal nodes.

Now there is a fight. Suppose the cell holds $Q = 0.9$ V and you want to write a 0. The write driver is pulling BL to ground through a big, strong transistor. The cell's own PMOS pull-up PU_L is pulling $Q$ to 0.9 V, because the cell still believes what it believes. Current flows from VDD through PU_L, through the access transistor AX_L, into the write driver, and down to ground. Whoever is stronger sets the voltage on $Q$.

The write succeeds if the driver can drag $Q$ far enough below the switching threshold of the other inverter that inverter R flips $QB$ high, at which point $QB$ turns PU_L off and PD_L on, and the cell's own feedback finishes the job and slams $Q$ to ground. So a write is not the driver forcing both nodes. It is the driver pushing one node just far enough that the loop's own positive feedback takes over and does the rest. The write margin is how much overkill you have in that push.

Two things follow immediately. Writing is faster than reading, because once the loop tips, the cell's own devices complete the transition at full speed rather than the driver having to charge everything. And writing is a contention operation, meaning it deliberately creates a temporary DC path from supply to ground inside the cell, which is why write energy per bit is higher than read energy per bit even though write is quicker.

4.2 The conflict, worked with transistor widths

Here is the tension, and it is the single best short answer to "what makes SRAM cell design hard."

For a read to be non-destructive, the access transistor must be weak compared with the cell's pulldown. During a read the bitline is at 0.9 V and the internal node holding 0 is connected to it through the access transistor. Charge flows in and lifts that node above ground. If the access transistor is strong and the pulldown weak, the node rises far enough to start turning on the other inverter, and the cell flips. That is a read disturb, and it is a silent data corruption caused by merely looking.

For a write to succeed, the access transistor must be strong compared with the cell's pull-up, because it has to drag the node holding 1 down against that pull-up.

The access transistor appears in both comparisons, in opposite directions. Two ratios name the two requirements.

$\text{cell ratio } \beta = \frac{(W/L)_{\text{pulldown}}}{(W/L)_{\text{access}}} \quad\text{wants to be LARGE, for read stability}$

$\text{pull-up ratio } \gamma = \frac{(W/L)_{\text{pull-up}}}{(W/L)_{\text{access}}} \quad\text{wants to be SMALL, for writability}$

Put widths on it, all at the same channel length. Take a pulldown of 200 nm, an access transistor of 130 nm, and a pull-up of 90 nm.

$\beta = \frac{200}{130} = 1.54 \qquad \gamma = \frac{90}{130} = 0.69$

A cell ratio around 1.5 and a pull-up ratio well under 1 is a healthy cell. Now suppose writes are failing at low voltage and somebody suggests the obvious fix, widening the access transistor to 200 nm.

$\beta = \frac{200}{200} = 1.00 \qquad \gamma = \frac{90}{200} = 0.45$

Writes got easier, exactly as intended. And the cell ratio fell to 1.00, which is well into read-disturb territory. You did not solve a problem, you moved it. Then somebody suggests widening the pulldown to 260 nm to restore $\beta$ to 1.3, and now the cell is larger in a structure replicated fifty million times, and you have traded away the density that was the reason to use 6T in the first place.

That is why the 6T cell has been essentially the same six transistors for thirty years with only the ratios being tuned. There is no clever rearrangement waiting to be found. There is a small, tightly constrained feasible region, and cell designers spend their careers inside it.

4.3 Why both margins collapse at low voltage, with the yield arithmetic

Now the part that most candidates state as a fact and cannot justify. Both margins shrink when the supply drops, and they shrink faster than linearly.

Two effects combine. First, the margins are fractions of the supply, so halving the supply roughly halves them in absolute millivolts before anything else happens. Second, and much worse, the thing eating those margins does not shrink. Transistor threshold voltages vary randomly from device to device because of random dopant fluctuation and line-edge roughness, and that variation has a standard deviation measured in millivolts that is a property of the device geometry, not of the supply. Call it $\sigma_{V_t} = 30$ mV, an illustrative but realistic figure for a small cell transistor.

So as the supply falls, the margin measured in millivolts falls while the noise measured in millivolts stays put. The margin measured in sigmas collapses.

Now ask how many sigmas you actually need, because this is where the number becomes shocking. Take an 8 MB last level cache.

$N_{\text{bits}} = 8 \times 1024 \times 1024 \times 8 = 67{,}108{,}864\ \text{bits}$

Suppose you want 99.9 percent of manufactured parts to have zero marginal cells before any repair. Then the expected number of failing bits per part must be about 0.001, so the per-bit failure probability must satisfy

$p \le \frac{0.001}{6.71 \times 10^{7}} = 1.5 \times 10^{-11}$

For a Gaussian, a one-sided tail probability of $1.5 \times 10^{-11}$ sits at about 6.6 standard deviations. So every one of those 67 million cells must have its margin exceed the mismatch distribution by 6.6 sigma, which at $\sigma_{V_t} = 30$ mV means roughly

$6.6 \times 30\ \text{mV} \approx 198\ \text{mV of margin required}$

Now put supply-dependent margins next to that requirement.

At 2.3 sigma the one-sided tail probability is about 0.01, so about 670,000 of your 67 million bits are broken. No redundancy scheme repairs that. The array simply does not work at 0.6 V.

That table is the answer to a question people give hand-wavy answers to. The array's minimum voltage is set by a six-sigma-plus requirement on a margin that is only a couple of hundred millivolts wide, against a mismatch distribution whose width does not scale. And because you need six sigma, the array Vmin is not where the typical cell fails. It is far above that, at the voltage where the worst cell out of sixty-seven million still works.

4.4 SRAM sets the minimum operating voltage of the chip

Logic is far more forgiving. A logic gate that is 20 percent slow than nominal is a timing problem you can fix by lowering the frequency. A cell whose noise margin has gone to zero is a functional failure at every frequency, exactly the asymmetry between setup and hold violations in section 5.6 of Digital Logic and Timing. And logic has only a few million critical instances, not sixty-seven million identical ones, so it needs far fewer sigmas.

The result is that a voltage domain containing an array can only drop to the array's Vmin, and that is almost always well above where the logic would still function. When DVFS Droop and Thermal talks about how low a DVFS operating point can go, this is what stops it. The lowest useful voltage of the whole chip is a bitcell property.

Three standard escapes exist and you should be able to name all three.

Dual rail. Give the arrays their own supply, held higher than the logic supply, so the logic can drop to 0.55 V while the arrays sit at 0.75 V. This works and is common. The cost is a second regulator or a second grid, level shifters at every boundary crossing per section 7.2 of Power Fundamentals and Clock Gating, and the area and complexity of two power grids in one block.

Assist circuits. Push the array's own Vmin down with extra circuitry, which is section 4.5.

A bigger, better cell. Offer an 8T or 10T cell with better margins at the cost of area, used selectively for the arrays that must run lowest.

4.5 Assist circuits

An assist is a circuit that temporarily and deliberately breaks the symmetry of the cell during exactly the operation that needs help, and gets out of the way afterwards. Each one buys margin somewhere and costs it somewhere else.

The phrase "half-selected cell" in that table deserves a definition because it is a favorite follow-up. When you write one word in a row, the wordline rises for the entire row, so every cell in that row has its access transistors on. The columns you are writing get driven bitlines. The columns you are not writing get bitlines left at the precharge level, which means those cells are being read whether you wanted to or not. Those are the half-selected cells, and they are exposed to the full read-disturb risk during a write. Any assist that weakens the cell to help the write, such as supply collapse, weakens the half-selected cells too, which is why cell supply collapse is applied per column and not per row.

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05.Part 5, array organization and the price of ports

5.1 One monolithic array is unbuildable

Try to build a 1 Mbit array as a single 1024 by 1024 block and both dimensions fail at once.

Bitlines. 1024 cells on a bitline gives $1024 \times 0.6\ \text{fF} = 614$ fF plus overhead, call it 620 fF. Develop to 100 mV takes

$t = \frac{620 \times 10^{-15} \times 0.1}{30 \times 10^{-6}} = 2.07\ \text{ns}$

which is six cycles at 3 GHz for the develop phase alone.

Wordlines. A 1024-cell wordline is a long, thin, resistive wire with capacitance distributed along it. A distributed RC line has delay proportional to $R_{total} C_{total}$, and both $R$ and $C$ scale with length, so wordline delay scales with the square of the length. Quadrupling the width multiplies the wordline delay by sixteen.

Power. Activating a 1024-cell wordline turns on 1024 cells and swings 1024 bitline pairs, to deliver perhaps 64 bits. You paid for sixteen times the bits you used.

5.2 Banking and subarrays, compared with numbers

The fix is to break the array into many small pieces and only activate one. The vocabulary is worth getting right because interviewers use the words precisely.

A subarray is the smallest physical block with its own bitlines, its own sense amplifiers, and its own precharge. Splitting into subarrays shortens wires and saves power, and it is invisible to the outside world other than through timing.

A bank is an independently addressable unit with its own decoder and its own data path, so two accesses to different banks can proceed in the same cycle. Banking is architecturally visible, because two accesses to the same bank collide and one must wait. That is a bank conflict, and your arbiter has to handle it.

Read the develop column. Going from a monolithic array to 256-row subarrays cut the dominant term by a factor of four, from 2.07 ns to 0.50 ns, which is the difference between a six-cycle array and a two-cycle array. That is the single biggest lever in array design and it costs decode logic, sense amplifier replication, and routing.

The costs are real and worth naming so the answer is not one-sided. Each subarray needs its own sense amplifiers, its own precharge devices, and its own local decode, and those repeat sixteen times. The global wires that carry addresses in and data out get longer because the array is now physically spread out. And the area overhead of a heavily subarrayed macro can be 30 to 50 percent above the raw bitcell area, which is why the ratio of bitcell area to total macro area, called array efficiency, is a headline number on a compiler datasheet and typically lands between 55 and 75 percent.

5.3 Aspect ratio and column multiplexing

Why not make every subarray extremely short and wide, so the bitlines are tiny? Because the wordline then becomes enormous and its RC delay goes as length squared. Why not extremely tall and narrow? Because the bitline capacitance goes back up. The compiler picks a shape that balances the two, and for typical processes a subarray lands somewhere between 128 and 512 rows and between 128 and 512 columns.

There is a second, purely physical constraint that decides the shape, and it surprises people. A sense amplifier is much wider than a bitcell. The cell is optimized to the absolute minimum pitch, perhaps 0.2 um wide. A sense amplifier is a matched differential pair with careful layout and it might need 1.6 um. So you physically cannot put one sense amplifier under every column. You put one under every eight columns and share it.

That sharing is the column multiplexer. An 8-to-1 column mux means each sense amplifier is switched between eight bitline pairs, and three address bits choose which.

Column multiplexing has three knock-on effects you should be able to state.

It wastes read power, because the wordline activated all eight columns' cells and swung all eight bitline pairs to deliver one bit. Designs that care recover some of this by only precharging or only enabling the selected columns.

It makes narrow writes awkward, because the half-selected cells of section 4.5 are exactly the seven columns you did not want.

And it gives you bit interleaving for free, which turns out to be the single most important structural defense against multi-bit soft errors. Section 7.10 collects the payoff.

5.4 The address decomposition, drawn

Make it concrete with a 64 KB macro built as 4 subarrays of 256 rows by 512 columns with an 8-to-1 column mux, delivering 64 bits per access.

$4 \times 256 \times 512 = 524{,}288\ \text{bits} = 64\ \text{KB} \qquad \frac{512\ \text{columns}}{8\text{-to-1 mux}} = 64\ \text{bits out}$

The macro holds $524288 / 64 = 8192$ words, so the address is 13 bits.

The placement of those three column-mux bits is a real design choice with real consequences. Putting them at the bottom of the address, as drawn, means consecutive words share a row, so a sequential burst of eight words hits one wordline and can be served from one activation, which is fast and low power. Putting them higher up spreads consecutive words across rows, which is worse for bursts but can be better for scattered access patterns. And whichever you choose determines which logical words are physically adjacent, which determines your soft-error multiplicity.

5.5 Multi-porting, and why area grows with the product

Now the most expensive thing you can ask an array for, and the place where interviewers separate people who have looked at a layout from people who have not.

A port is a way in or out. A single-port array can do one thing per cycle. A 2-read 1-write array can do three things per cycle. The naive expectation is that three ports cost three times one port. They cost far more, and the reason is geometric.

An SRAM bitcell is wire limited, not transistor limited. Its width is set by how many vertical wires must pass through it, meaning bitlines plus power. Its height is set by how many horizontal wires must pass through it, meaning wordlines plus ground straps. The transistors themselves fit in the space the wires leave.

Now count wires per port. A write port needs a differential bitline pair, two vertical tracks, plus one wordline, one horizontal track. A read port in a decoupled-read cell needs one single-ended bitline, one vertical track, plus one wordline, one horizontal track. Area is width times height, so it is a product of two sums, and that is where the quadratic comes from.

Tabulate it with a simple model where width equals 2 supply tracks plus one track per read bitline plus two per write bitline pair, and height equals 1 contact track plus one track per wordline.

Twelve ports costs twenty-nine times the area, not twelve times. The model is crude and real cells do better than a pure product because some tracks are shared, but the scaling is right and the message is right. Area grows roughly with the square of the port count, not linearly.

And area is not even the worst of it. More ports means longer wordlines and more bitlines hanging on each internal node, which means each port is individually slower. So a heavily ported array is simultaneously enormous and slow, which is precisely the wrong combination for a structure that sits in the execute loop.

5.6 The four ways to fake more ports

Because true multi-porting is so brutal, real designs almost never buy it directly above two or three ports. Four alternatives exist and a good answer names all four with their failure modes.

Banking with conflict handling. Build many independent single-port banks and hope simultaneous accesses land in different banks. Cheap in area, and it works well when the access pattern is spread out. It fails when two accesses collide, so you need arbitration, stall logic, and possibly replay. The cost is not area, it is a variable-latency array, which is much harder for a scheduler to plan around. This is why bank conflicts show up as a performance counter.

Double pumping, also called time multiplexing. Run the array at twice the core clock and perform two accesses per core cycle, presenting a virtual dual-port array. Costs almost no area. Fails because the array now has to close timing at half the cycle, and section 3.5 showed that the develop phase already eats most of a cycle. So double pumping works for small, short-bitline arrays and does not work for a large cache. It also creates a second clock domain inside the block with all the discipline of Clocking Reset and Domain Crossing.

Replication. Keep two or four identical copies of the data. Each copy is a cheap 1R1W array, reads go to whichever copy is free, and writes go to all copies. Area is $n$ times the single-copy area, which for the numbers above beats true porting badly. An 8R1W true array in the model is 10 bitline tracks by 9 wordline tracks, or 120 units, 15 times a 6T cell. Four replicated 2R1W arrays are $4 \times 24 = 96$ units, 12 times, and every copy is individually fast because its wires are short. The cost is write bandwidth, since every write must reach every copy, and a coherence-like problem if writes and reads to different copies can be reordered. Clustered register files in the published literature, such as the Alpha 21264, took exactly this route.

Hierarchical or clustered organization. Split the consumers into clusters, give each cluster its own smaller array, and pay a penalty when a cluster needs a value that lives elsewhere. This is replication plus locality, and it converts an area problem into a scheduling problem.

5.7 Register file array design

A register file is an SRAM array pushed to the opposite extreme from a cache, and topic 139 asks about it specifically. Get the contrast straight and it is memorable.

A physical register file in a wide out-of-order core might be 384 entries of 64 bits, with something like eight read ports and four write ports to feed and retire from multiple execution ports. Count the bits.

$384 \times 64 = 24{,}576\ \text{bits} = 3\ \text{KB}$

Three kilobytes. Now apply the porting multiplier from 5.5, where 8R4W came out at 29 times a plain 6T cell.

$3\ \text{KB} \times 29 \approx 87\ \text{KB equivalent of 6T bitcell area}$

The register file holds three kilobytes and occupies more silicon than a 64 KB L1 cache. That number, worked out loud, is one of the most convincing things you can say about why register file design is its own discipline and why Execution Units spends so long on bypass networks and clustering. Every bypass path you build is a read port you did not have to buy.

The design differences follow from the extreme.

The 8T cell with a decoupled read port deserves its own paragraph because it resolves the conflict of section 4.2 by construction. Add two transistors forming a small read buffer whose gate is the storage node and whose output drives a dedicated read bitline. Now a read never touches the storage node at all, it only senses it through a gate, so there is no read disturb and no read stability constraint. The access transistors then only have to satisfy the write requirement, which means they can be made strong and the cell can operate at a much lower voltage. The cost is the two extra transistors and the extra bitline track, which is why 8T is normal in register files and in low-voltage arrays and too expensive in a large cache.

The other register file specifics worth naming. Bitlines are kept extremely short by splitting the file into small local groups with local sense and a hierarchical global bitline, because a one-cycle read leaves no time for a long develop. Reads are frequently single ended because the bitline is short enough that noise immunity is not the binding constraint and a second track per port is unaffordable. And protection is minimal, because there is no spare cycle for a syndrome and the file is small enough that its contribution to the chip's soft error rate is modest. Where protection is required, the usual answer is parity plus a machine check rather than inline correction, or a radiation-hardened cell that stores the bit redundantly inside the cell itself.

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06.Part 6, how arrays fail

Arrays are the most failure-prone structures on a die, and for two completely different reasons that need completely different fixes. Keeping them apart is half the battle.

6.1 Soft errors, from the physics up

A soft error is a stored bit changing value with nothing physically broken. Rewrite the location and it is fine. The cell is not damaged, it was simply knocked over.

The mechanism is ionizing radiation. Two sources matter on Earth.

Alpha particles from package materials. Trace radioactive contaminants in solder, molding compound, and interconnect metals, historically lead-210 and thorium and uranium daughters, emit alpha particles of about 5 MeV. Purified materials cut this enormously and it is largely a solved manufacturing problem, but it never goes to zero.

Cosmic ray secondaries. A primary cosmic ray hits the upper atmosphere and produces a shower. What reaches sea level in quantity is high-energy neutrons. A neutron is uncharged so it deposits no charge directly, but it can strike a silicon nucleus and shatter it, and the resulting charged fragments do the ionizing. The sea-level flux above 10 MeV is roughly 13 neutrons per square centimetre per hour at New York City in the standard JEDEC reference, rises by roughly a factor of three to four at Denver's altitude, and by a factor of a few hundred at commercial aircraft altitude. That is why avionics and high-altitude installations have visibly worse error rates and why the flux is a specified environmental parameter and not a constant of nature.

Now the arithmetic that shows why this is not a marginal effect. Take a 5 MeV alpha particle. It takes about 3.6 eV of deposited energy to create one electron-hole pair in silicon, so the total number of pairs along the track is

$\frac{5 \times 10^{6}\ \text{eV}}{3.6\ \text{eV}} = 1.39 \times 10^{6}\ \text{pairs}$

and the total charge liberated is

$1.39 \times 10^{6} \times 1.6 \times 10^{-19}\ \text{C} = 2.2 \times 10^{-13}\ \text{C} = 222\ \text{fC}$

spread over a track of roughly 25 um, so about 9 fC per micron. Only the charge generated in and near the depletion region is collected quickly enough to matter, so the collected charge might be a few femtocoulombs to a few tens.

Compare that with what it takes to flip a cell. The critical charge $Q_{crit}$ is the charge that must be injected into a storage node to push it past the middle crossing of section 2.3 before the cell's own restoring current can fight it off. Approximate it as the node capacitance times the supply.

$Q_{crit} \approx C_{node} \times V = 0.7\ \text{fF} \times 0.8\ \text{V} = 0.56\ \text{fC}$

Perhaps one to two femtocoulombs once you account for the cell's restoring current during the strike. Against several femtocoulombs collected, it is not a close contest. The strike wins comfortably, and it has been winning by a larger margin every process generation, because $Q_{crit}$ falls with node capacitance and supply voltage while the physics of the particle does not change at all.

The industry unit is the FIT, one failure per $10^9$ device-hours. Per-bit raw SRAM soft error rates in public literature have run from around $10^{-3}$ FIT per bit in planar processes down toward $10^{-4}$ FIT per bit in FinFET generations, where the fin geometry presents a much smaller collection volume. Take $10^{-3}$ FIT per bit as an illustrative planar figure and put it on an 8 MB cache.

$67.1 \times 10^{6}\ \text{bits} \times 10^{-3}\ \frac{\text{FIT}}{\text{bit}} = 67{,}109\ \text{FIT}$

$\text{MTBF per part} = \frac{10^{9}}{67{,}109} = 14{,}900\ \text{hours} \approx 1.7\ \text{years}$

One unprotected cache error every one and a half years per device sounds almost tolerable until you multiply by a fleet. Across 100 million shipped devices, the fleet rate is

$\frac{67{,}109 \times 10^{8}}{10^{9}} = 6{,}711\ \text{failures per hour} \approx 1.9\ \text{per second}$

Two silent data corruptions per second across the installed base, forever. That is the number that makes ECC non-negotiable, and it is worth being able to produce on demand because it converts an abstract reliability argument into a product argument. Even at the FinFET figure of $10^{-4}$ FIT per bit it is one every five seconds.

6.2 What shrinking cells does, in both directions

The intuitive answer is that smaller cells are more vulnerable, and that is half right in a way worth understanding precisely, because the full picture explains the single most important structural defense in Part 7.

Smaller is worse, because $Q_{crit}$ falls. Node capacitance shrinks with the device and supply voltage shrinks with the process, and $Q_{crit}$ is roughly their product, so it falls on both counts. A strike that would once have been shrugged off now flips the cell.

Smaller is better, because the cross section falls. A cell that occupies a quarter of the area presents a quarter of the target to an incoming particle. Fewer strikes land on it at all.

Those two effects have largely cancelled, and per-bit soft error rates have been roughly flat to slowly declining for several generations, with FinFET giving a real step improvement because the conducting channel is a thin fin sitting above the bulk rather than a large junction embedded in it, so most of the liberated charge never gets collected.

But two things did get worse and both matter.

Per-chip rates rose, because bit counts exploded. Flat per-bit multiplied by ten times the bits is ten times the failures.

Error multiplicity rose, and this is the dangerous one. As cells shrank, a single particle track that once covered one cell now covers three or four adjacent cells, and the charge it deposits is shared among them. The result is a multi-cell upset, or MCU, where one event flips several physically adjacent bits at once.

That single change breaks the standard defense, because the standard code corrects one error per protected word and merely detects two. If those four adjacent cells happen to be four bits of the same logical word, the code sees a four-bit error, which it neither corrects nor is guaranteed to detect, and it may confidently miscorrect and hand you data that is now worse than what it received. Section 7.10 is the fix and it is purely a layout decision, which is why the address decomposition of section 5.4 mattered.

6.3 Hard errors, redundancy, and repair

A hard error is a permanently broken cell, from a manufacturing defect, a stuck contact, a shorted bitline, or wearout mechanisms over the product's life. Rewriting does not help. This is a yield problem, not a reliability problem, and it is fixed by physical redundancy rather than by codes.

Work the yield to see why redundancy is universal. Take a per-bit defect probability of $2 \times 10^{-9}$, an illustrative figure. A 512 Kbit macro then has an expected defect count of

$\lambda_{\text{macro}} = 524{,}288 \times 2 \times 10^{-9} = 1.05 \times 10^{-3}$

so 99.9 percent of individual macros are perfect. Fine. But a chip contains many macros. With 200 of them,

$\lambda_{\text{chip}} = 200 \times 1.05 \times 10^{-3} = 0.21 \qquad Y = e^{-0.21} = 0.81$

Nineteen percent of parts thrown away because of single broken bits in arrays. That is an unshippable yield loss and it is why every serious array ships with spares.

Now add two spare columns per macro, so a macro only fails if it has more than two defects. For a Poisson with $\lambda = 1.05 \times 10^{-3}$ the probability of three or more is about $\lambda^3/6 = 1.9 \times 10^{-10}$, and across 200 macros that is $3.9 \times 10^{-8}$. Yield goes from 81 percent to essentially 100 percent for a few percent of extra array area. That is one of the best returns on area anywhere in chip design, and it is why redundancy is not optional.

The mechanism is worth naming precisely because it is a DFT conversation as much as a design one. Memory BIST is a small state machine attached to the array that writes and reads known patterns at speed and reports failing addresses. Built-in redundancy analysis takes the failing address list and computes a repair solution, meaning which spare row or column should replace which failing one. Built-in self repair then programs that solution permanently, historically by blowing laser or electrical fuses, so the repair is applied automatically at every subsequent power-up by remapping the decoder. All three run at wafer test, and a modern part carries a fuse array whose only job is holding repair solutions. DFT and Silicon Debug carries the test-side treatment.

Two limits are worth knowing. Redundancy repairs a small number of localized defects and cannot help with a systematically weak array, and the spare granularity matters, since a spare column repairs one bad bit in every row of a subarray while a spare row repairs a whole bad wordline, so you generally want both.

6.4 The three outcomes, and why one of them is the enemy

Every error event ends in one of exactly three states, and the industry vocabulary for them is used constantly.

SDC is the enemy. A crash is recoverable, annoying, and diagnosable. A wrong answer that propagates into a filesystem, a financial calculation, or a training run is none of those. So the entire design of Part 7 is organized around converting potential SDCs into CEs where possible and into DUEs where not, and the value of a code is measured much more by how few SDCs it leaves than by how many errors it corrects.

That framing also explains a design decision that otherwise looks lazy. Some structures get no protection at all, and that is correct rather than negligent, because an error in them cannot produce an SDC. Section 7.8 collects those cases.

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07.Part 7, error correcting codes from the ground up

This is the part to be strongest on, and it is best built from a tiny concrete example rather than from definitions.

7.1 Redundancy, distance, and what a code actually is

Send one bit down a wire. It arrives as a 0. Is it correct?

You cannot possibly tell, and the reason is not subtle. There are two possible messages and two possible received values, and every received value is a legal message. There is no observation that distinguishes "the sender sent 0" from "the sender sent 1 and it flipped." Detection is impossible in principle, not merely hard.

So send it three times. The sender is only allowed to transmit $000$ or $111$. Those two are the codewords. The other six three-bit strings are illegal. Now if you receive $010$, you know something went wrong, because $010$ is not a legal transmission. And you can do better than know. $010$ differs from $000$ in one position and from $111$ in two, so if you believe single errors are much more likely than double errors, $000$ is the better bet. Take the majority vote and you have corrected the error.

Draw all eight three-bit strings as the corners of a cube.

Only now do the definitions mean something. The Hamming distance between two binary strings is the number of positions where they differ. The minimum distance $d$ of a code is the smallest Hamming distance between any two of its codewords. And the two facts that govern everything follow directly from the picture.

$\text{to DETECT } s \text{ errors you need } d \ge s + 1$

$\text{to CORRECT } t \text{ errors you need } d \ge 2t + 1$

Detection needs $d \ge s+1$ because $s$ flips must never be able to land you exactly on another codeword. Correction needs $d \ge 2t+1$ because the spheres of radius $t$ around each codeword must not overlap, and two spheres of radius $t$ are disjoint only if their centres are more than $2t$ apart.

The repetition code has $d = 3$, so it corrects $t = 1$ or detects $s = 2$, and notice the "or." You choose. If you use the code to correct single errors, then a double error like $000 \to 110$ lands in B's sphere and you will confidently "correct" it to $111$, producing three wrong bits from two. If instead you decline to correct and only report legality, you catch every double error. A code's distance is a fixed budget and correction and detection spend from the same budget. That single sentence explains the entire structure of SECDED in section 7.4, and it is the conceptual crux of this Part.

The price here is brutal. Three bits sent for one bit of data is a code rate of $1/3$ and an overhead of 200 percent. Nobody pays that for memory. The rest of Part 7 is about getting the same distance far more cheaply, and the way you do it is by protecting many data bits together instead of one at a time.

7.2 Parity, the one-bit code

The cheapest possible code adds a single bit chosen so the total number of ones is even. That is even parity, and the parity bit is simply the XOR of all the data bits.

Take the byte $0110\,1011$. It has five ones, which is odd, so the parity bit is 1 and the transmitted nine bits are $0110\,1011\,|\,1$ with six ones total. On receipt, XOR all nine bits. If the answer is 0 the word is consistent, if it is 1 something flipped.

Flip bit 3 in transit, giving $0111\,1011\,|\,1$ with seven ones. XOR of all nine is 1. Detected.

Now flip bits 3 and 5, giving $0111\,1111\,|\,1$ with eight ones. XOR of all nine is 0. Not detected. The word looks perfectly healthy and you will use it.

That behaviour is exactly what the distance rule predicts. Any two parity-protected words differ in at least two positions, one data bit plus the parity bit that follows it, so $d = 2$. From $d \ge s+1$ you get $s = 1$, meaning detect one error. From $d \ge 2t+1$ you get $t = 0$, meaning correct nothing. Parity detects any odd number of errors and is blind to any even number, and corrects nothing at all.

The overhead is negligible. One bit on 64 is 1.6 percent. The hardware is one XOR tree. So the question is not whether parity is cheap, it is when detection without correction is enough.

The rule is short and it is the answer to a very common interview question. Parity suffices exactly when a known-good copy of the data exists somewhere else and you can afford to go get it.

The canonical case is an L1 instruction cache. Instructions are read-only from the cache's point of view, so every line in it is clean, which means an identical copy exists in L2 or memory. Protect it with parity per some granule. On a parity error, do not correct, do not panic, just invalidate the line, treat the access as a miss, and refetch. The instruction stream is unaffected apart from a few tens of cycles. Correction machinery would buy nothing over a mechanism the pipeline already has, because refill on a miss is the front end's ordinary behaviour per Front End and Branch Prediction.

The same argument covers clean lines in a data cache, a TLB whose entries can be re-walked from the page tables per Virtual Memory and Memory Ordering, and any structure that is a cached copy of something authoritative elsewhere.

Where parity fails is the moment the array holds the only copy. That is section 7.4's argument for write-back caches, and it is the reason SECDED exists.

7.3 Hamming's construction, derived rather than quoted

Repetition is too expensive because it protects one bit at a time. The insight that fixes it is to protect $k$ data bits together with $r$ check bits and to make each check bit answer a different question about the whole word.

Before building anything, count what the check bits have to accomplish. After receiving a word, you must be able to distinguish these outcomes:

• no error at all, which is one outcome
• an error in any one of the $k + r$ transmitted positions, which is $k + r$ outcomes

That is $k + r + 1$ distinct answers you need to produce. The $r$ check bits, recomputed and compared, give you $r$ bits of information, which can name at most $2^r$ things. So

$2^r \ge k + r + 1$

That inequality is not a formula to memorize, it is a counting argument, and being able to derive it in ten seconds at a whiteboard is worth more than knowing the answer. It says nothing more than that $r$ yes-or-no questions must be enough to name every possible outcome.

Solve it for $k = 4$. Try $r = 2$, giving $4 \ge 7$, false. Try $r = 3$, giving $8 \ge 8$, true and exactly tight. So four data bits need three check bits, for a seven-bit codeword. That is the (7,4) Hamming code, and its tightness makes it a perfect code in the sphere-packing sense of section 7.1.

Now the construction, which is where Hamming's actual cleverness lives. Number the seven positions 1 through 7. Put the check bits at the positions that are powers of two, so positions 1, 2, and 4, and put the data bits everywhere else, so positions 3, 5, 6, and 7. Then define check bit $p_j$ at position $j$ to cover exactly those positions whose binary representation has the bit for $j$ set.